k2/rv64 [ Modules ]
NAME
rv64
FUNCTION
This module provides the RISC-V emulator.
rv64/rv64_cause_s, rv64/rv64_cause_t [ Types ]
NAME
struct rv64_cause_s
rv64_cause_t
FUNCTION
This structure models the mcause/scause registers found in the RISC-V privileged ISA specs.
SOURCE
typedef union rv64_reason_u {
rv64_int_reason_t i;
rv64_exc_reason_t e;
} rv64_reason_t;
typedef struct rv64_cause_s {
bool interrupt;
rv64_reason_t reason;
} rv64_cause_t;
rv64/rv64_exc_reason_e, rv64/rv64_exc_reason_t [ Types ]
NAME
enum rv64_exc_reason_e
rv64_exc_reason_t
FUNCTION
In the event of a synchronous trap, these mcause reason codes will indicate the source of the trap.
SOURCE
typedef enum rv64_exc_reason_e {
INS_ADDR_MISALIGNED = 0,
INS_ACCESS,
ILLEGAL_INS,
BREAKPOINT,
LD_ADDR_MISALIGNED,
LD_ACCESS,
ST_ADDR_MISALIGNED,
ST_ACCESS,
U_ECALL,
S_ECALL,
reserved_00,
M_ECALL,
INS_PAGE_FAULT,
LD_PAGE_FAULT,
reserved_01,
ST_PAGE_FAULT,
DOUBLE_TRAP,
reserved_02,
SOFTWARE_CHECK,
HARDWARE_ERROR,
EMULATOR_CHECK = 24, // emulator specific
EMULATOR_RESET, // emulator specific
} rv64_exc_reason_t;
rv64/rv64_int_reason_e, rv64/rv64_int_reason_t [ Types ]
NAME
enum rv64_int_reason_e
rv64_int_reason_t
FUNCTION
In the event of an external interrupt, these mcause reason codes will indicate the source of the interrupt.
SOURCE
typedef enum rv64_int_reason_e {
S_SOFTWARE_INT = 1,
M_SOFTWARE_INT = 3,
S_TIMER_INT = 5,
M_TIMER_INT = 7,
S_EXTERN_INT = 9,
M_EXTERN_INT = 11,
M_CTR_OVERFLOW = 13,
} rv64_int_reason_t;
rv64/rv64_priv_e, rv64/rv64_priv_t [ Types ]
NAME
enum rv64_priv_e
rv64_priv_t
FUNCTION
A 2-bit field which specifies the current processor operating mode. User mode is the least privileged, while machine mode is the most privileged. Some RISC-V processors implement a supervisor mode, while others do not.
SOURCE
typedef enum rv64_priv_e {
PRIV_USER = 0,
PRIV_SUPERVISOR = 1,
_PRIV_HYPERVISOR = 2,
PRIV_MACHINE = 3
} rv64_priv_t;
rv64/rv64_s, rv64/rv64_t [ Types ]
NAME
struct rv64_s
rv64_t
FUNCTION
This structure records the entire state of the RISC-V virtual processor.
SOURCE
typedef struct rv64_s {
uint64_t x[32];
uint64_t pc;
rv64_priv_t mode;
rv64_status_t status;
uint64_t mtvec;
uint64_t mepc;
rv64_cause_t mcause;
uint64_t mtval;
uint64_t mtval2;
uint64_t mideleg;
uint64_t medeleg;
uint64_t mie;
uint64_t mip;
uint64_t stvec;
uint64_t sepc;
rv64_cause_t scause;
uint64_t stval;
bool critical_error;
uint64_t critical_pc; // emulator specific
rv64_priv_t critical_target; // emulator specific
rv64_cause_t critical_cause; // emulator specific
uint64_t critical_val; // emulator specific
uint64_t critical_val2; // emulator specific
bool trap_taken;
} rv64_t;
rv64/rv64_status_s, rv64/rv64_status_t [ Types ]
NAME
struct rv64_status_s
rv64_status_t
FUNCTION
This structure models the fields found in the mstatus/sstatus registers.
NOTE These are not in bit-packed order, but in the order they're documented in the RISC-V Instruction Manual, Volume I.
SOURCE
typedef struct rv64_status_s {
bool mdt; // machine double trap
bool sdt; // supervisor double trap
rv64_xlen_t sxl; // technically read-only for our implementation
rv64_xlen_t uxl;
bool mprv; // defined for paged memory, but also valid for
bool mxr; // segmentation as well.
bool sum;
bool tvm;
bool tsr;
rv64_priv_t mpp; // machine previous privilege
bool spp; // supervisor previous privilege
bool mpie; // machine previous int enable
bool spie; // supervisor previous int enable
bool mie; // machine int enable
bool sie; // supervisor int enable
} rv64_status_t;
rv64/rv64_xlen_e, rv64/rv64_xlen_t [ Types ]
NAME
enum rv64_xlen_e
rv64_xlen_t
FUNCTION
A 2-bit field often found in mstatus/sstatus registers used to configure the CPU's operating data path width.
SOURCE
typedef enum rv64_xlen_e {
XLEN_NOT_SUPPORTED = 0,
XLEN_32BITS = 1,
XLEN_64BITS = 2,
XLEN_reserved = 3
} rv64_xlen_t;
rv64/rv64_xreg_at, rv64/rv64_xreg_at_put [ Functions ]
[ Top ] [ rv64 ] [ Functions ]
NAME
rv64_xreg_at
rv64_xreg_at_put
SYNOPSIS
* uint64 rv64_xreg_at(rv64_t* rv, int rs) * void rv64_xreg_at_put(rv64_t* rv, int rd, uint64_t v)
FUNCTION
rv64_xreg_at retrieves the current value of a CPU register. If you attempt to read X0, it will always report zero, as specified by the ISA specs.
rv64_xreg_at_put updates a CPU register with a new value.
INPUTS
rv Pointer to an rv64_t structure. rs Source register for reading. rd Destination register for writing. v New 64-bit value. RESULT For rv64_xreg_at(), the current value of the source register.
SOURCE
static inline uint64_t rv64_xreg_at(rv64_t* rv, int s) { return (s == 0) ? 0 : rv->x[s]; } static inline void rv64_xreg_at_put(rv64_t* rv, int d, uint64_t v) { if (d) { rv->x[d] = v; } }
rv64/rv64_xreg_e, rv64/rv64_xreg_t [ Types ]
NAME
enum rv64_xreg_e
rv64_xreg_t
FUNCTION
This enumeration lists all the RISC-V user-mode registers accessible from the RV64IM instruction set.
Both X0-X31 and their C ABI synonyms (e.g., RA for X1, SP for X2, etc.) are provided
SOURCE
typedef enum rv64_xreg_e {
X0, X1, X2, X3, X4, X5, X6, X7,
X8, X9, X10, X11, X12, X13, X14, X15,
X16, X17, X18, X19, X20, X21, X22, X23,
X24, X25, X26, X27, X28, X29, X30, X31,
ZERO = 0, RA, SP, GP, TP, T0, T1, T2,
S0, S1, A0, A1, A2, A3, A4, A5,
A6, A7, S2, S3, S4, S5, S6, S7,
S8, S9, S10, S11, T3, T4, T5, T6
} rv64_xreg_t;